A technology has been known in which a top portion of a polycrystalline silicon layer included in a control gate electrode of a nonvolatile semiconductor memory device is partially silicided to reduce an electrical resistance of the control gate electrode.
In a case where the top portion of the control gate electrode is partially silicided, the thickness of the silicide layer may problematically become uneven because the reaction rate varies depending on the location of the control gate electrodes.